n hcountreg >=610 and hcountreg < 630

else '1';

hz_temp <= '1' when hcountreg = 650 else '0';

lcd_hz <=hz_temp or rst_seq;

end block hcount;

diff : block

signal inputrega : std_logic;

signal inputregb : std_logic;

begin

process(clk_seq)

begin

if clk_seq'event and clk_seq='1' then

inputregb <= inputrega;

inputrega <= not lcd_hs;

end if;

end process;

clken_vcount <= not inputregb and inputrega;

end block diff;

vcount : block

signal vcountreg : std_logic_vector(9 downto 0);

signal vz_temp : std_logic;

signal lcd_vz : std_logic;

begin

process (clk_seq,lcd_vz)

begin

if(lcd_vz='1')then

vcountreg <= (others => '0');

elsif clk_seq'event and clk_seq = '1' then

if clken_vcount = '1' then

vcountreg <= vcountreg +1;

end if;

end if;

end process;

lcd_vb <= '0' when vcountreg >=600 and vcountreg < 615

else '1';

lcd_vs <='0' when vcountreg >=607 and vcounreg < 610

else '1';

vz_temp <= '1' when vcountreg = 615 else '0';

lcd_vz <= vz_temp or rst_seq;

end block vcount;

pix_clk <=clk_seq;

lcd_dataen <=lcd_hb and lcd_vb;

lcd_hs_out <=lcd_hs;

lcd_vs_out <=lcd_vs;

end rtl_seq_gen;

这种用VHDL产生扫描时序的方法简单、易读，并且易于修改。在代码中只须修改一些时序参数就能产生任意时序的波形，具有很好的可重用性。用FPGA Express 3.5半VHDL代码综合后，通过Foundation 3.1i进行布局和布线，用Foundation提供的门级仿真工具产生的行扫描时序仿真图如图4所示。

采用FPGA技术设计的AMLCD控制器，大大减少了电路板的尺寸，同时增加了系统可靠性和设计灵活性。这种用VHDL语言实现现行场扫描时序生成器的方法，具有简便。易读和可重用性强的特点。该AMLCD控制器已用Xilinx公司的SpartanII系列器件XC2S50实现，并在飞机座舱图形显示系统中实现应用。